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AN1078/0998 1/12 application note st7 timer pwm duty cycle switch for true 0% or 100% duty cycle by microcontroller division applications introduction this application note presents a program that uses the 16-bit timer of the st7 in pwm output mode. the program can be used to perform a hot switch from one duty cycle to another and obtain a true fixed period and true duty cycle percentage values between 0% and 100%. the example program in this application note has been developed for the st7gp family (st72251g1 and g2). you have to choose your st7 device at the beginning of the program using one of the several a#defineo statements provided. in this application, we chose to use a st72251g2. 1 pwm duty cycle 1.1 definitions n pwm means pulse width modulation. pwm mode enables the generation of a signal with a frequency and pulse length determined by the value of the timer a output compare 1 and timer a output compare 2 registers (taoc1r and taoc2r) of the st7 16 bit timer. the pwm output pin is ocpm1_a (timer a output compare 1). n x% duty cycle means that the pulse length represents x% of the period. n fcpu means cpu frequency (in this case 8 mhz) n a timer tick is a timer clock cycle (here 1 timer tick is 1 m s because fcpu/8=1 mhz). n output level 1 (olvl1) is a timer a control register 1 (tacr1) bit which is copied to the ocmp1 pin whenever a successful comparison occurs with the taoc1r register. then the taoc1e (timer a output compare 1 enable) bit is set in the tacr2 register. n with the olvl1 bit, we select the level to be applied to the ocmp1 pin after a successful comparison with the taoc1r register. with the olvl2 bit in the tacr1 register the comparison is with the taoc2r register. for more precise details on how the pwm runs, please refer to the pwm chapter in the 16-bit timer section of the datasheet. 1
2/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle 1.2 16 bit timer operation in pwm mode the pwm mode uses the complete timer a output compare 1 function plus the taoc2r register. an output compare 2 event causes the counter to be initialized to fffch which is the counter reset value. so after each period, the counter is reset to fffch. as shown in figure 1 the pulse length and the period that you can see are 5 timer ticks longer than the values you have loaded in the taoc1r and in taoc2r registers. figure 1. general frame without correction of the 5 time tick shift the minimum value available for the pulse length is programmed when you load the counter reset value in taoc1r (fffch). instead of having 0% duty cycle, the pwm mode feature produces a 1 timer tick pulse as shown in figure 2. figure 2. 0% duty cycle minimum value with oc1r=fffch=counter reset value when you set the pulse length equal to the period in order to have a 100% duty cycle, you have a pulse of one cpu tick as shown in figure 3. this could be useful for performing an ex- ternal synchronization. however if you want a really 100% duty cycle you can use the true routine described below. counter 34dd fffc fffd fffe ffff 0000 0001 2100 2101 olvl2 olvl1 ocmp1_a compare2 compare1 note: taoc1r=2100h, taoc2r=34ddh, olvl1=0, olvl2= 1 olvl1 pulse length =oc1r+5 counter 34dd fffc fffd fffe 2ed0 2ed1 2ed2 34dd fffc olvl2 olvl1 ocmp1_a compare2 compare1 compare2 note: taoc1r=fffch, taoc2r=34ddh, olvl1=0, olvl2= 1 compare1 olvl2 olvl1 olvl1 olvl1
3/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle figure 3. 100% duty cycle with taoc1r=taoc2r=period 1.3 program objectives the three following objectives are achieved by our true routine. the routine is called in the aext0_rto interrupt routine which changes the duty cycle value. the ainit_proga routine loads the desired period value minus five in the taoc2r register to obtain the correct timer tick value for the period. 1.3.1 decrement the pulse length by 5 timer ticks to obtain the correct timer tick value for the pulse length, we subtract 5 timer ticks before loading them in the taoc1r register. 1.3.2 obtain a true 0% duty cycle on the following program the atrueo routine rectifies the 1 timer tick glitch by resetting the olvl2 bit (olvl2=olvl1=0) of the tacr1 register in order to have a true 0% duty cycle. this is done by comparing the pulse length value with 0000h. 1.3.3 obtain a true 100% duty cycle on the following program the atrueo routine produces a true 100% duty cycle by setting olvl1 bit (olvl1=olvl2=1) of the tacr1 register in order to suppress the pulse of one cpu tick. this is done by comparing the pulse length value with the period length (constant defined at the beginning of the program). note : you can use the program to switch to different duty cycles by looping through the fol- lowing series of constants using the aext0_rto interrupt routine: 100%, 75%, 50%, 25%, 0%, 25%... the switch is caused by a falling edge on pa0. pa0 is configured as an input with pull up and interrupt, a low level applied on this pin causes an external interrupt. by default when you run the program you have a 100% duty cycle with the one timer tick pulse as explained above. counter 34dc 34dd fffc fffd 2ed0 2ed1 2ed2 34dd fffc olvl2 ocmp1_a note: taoc1r=34ddh, taoc2r=34ddh, olvl1=0, olvl2= 1 olvl2 1 cpu tick 1 cpu tick olvl2 olvl2 olvl1 olvl1
4/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle 2 flowcharts figure 4. main routine (for st72251g2) the falling edges on pa0 allow you to switch from one duty cycle value to another by exe- cuting the aext0_rto interrupt routine. taocr1=taocr2=desired period-5 (no correction so 1 cpu tick pulse) falling edge on pa0 state=1001 0000 so 100% period (true 100%) state=1000 1000 75% period state=1000 0100 50% period falling edge on pa0 state=1000 0010 25% period state=1000 0001 0% period falling edge on pa0 state=0000 0010 25% period falling edge on pa0 state=0000 0100 50% period falling edge on pa0 state=0000 1000 75% period falling edge on pa0 falling edge on pa0 falling edge on pa0
5/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle figure 5. the aext0_rto interrupt routine (here for a st72251g2) to use the duty cycle values in increasing or decreasing order, we use the up/down bit of the astateo 8-bit variable. the up/down bit is the seventh bit of astateo. the others are used to code the duty cycle value. look at the following code meaning with x =up/down: n 100% duty cycle -> x001 0000 n 75% duty cycle -> x000 1000 n 50% duty cycle -> x000 0100 n 25% duty cycle -> x000 0010 n 0% duty cycle -> x000 0001 up/down=1? 100% ? 0% ? iret iret clear ostateo y y y n n n sla state bset up/down falling edge on pa0 tests of ostateo value call the true routine load next duty cycle value (75%) in ostateo iret sra state
6/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle figure 6. the atrueo routine flowchart this routine performs the 5 timer tick shift, and generates a true 0% or 100% duty cycle using the olvl1 and olvl2 bits. olvl1=1 0% ? load of taoc1r and subtract 5 timer ticks olvl2=0 y y n n 100% ? ret ret ret call the true routine
7/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle 3 software the assembly code given below is guidance only. the complete software with all the files can be found in the software library. st7/ ; the first line is reserved ; for specifying the instruction set ; of the target processor ;*************** ********************************************************* ; title: pwm.asm ; author: ppg microcontroller application team ; description: demonstration program ; for the timer peripheral used in pwm configuration. ; this program illustrates the timer's behavi our when it is ; configured in pwm mode. ; a pwm signal will be generated on ocmp1_a pin. the length ; of the pulse is located in the ocr1 register while the ; signal's period is in the ocr2 register. ; we begin by a normal 100% duty cycle which has a one cpu tick ; pulse by default. ; at each falling edge on pa0,(cf st72 trainin g board ; button) you change the duty cycle by loopin g through this ; sequence of values:true 100% 75% 50% 25% 0% 25% 50% 75% ; \_______________________| ; the interrupt produced by the icf1 bit at the end of each ; period is used to toggle pb7. ;*************** ********************************************************* title opwm.asmo ; this title will appear on each page of the listing file motorola ; this directive forces the motorola ; format for the assembly (default) #include ost72251.inco; include st72251 registers and memory ;*************** ******************************************************** ; variables, constants defined and referenced locally ; you can define your own values for a local reference here ;*************** ******************************************************** #define up/down 7 ;to use sequence in increa sing or decrasing order #define olvl1 0 ; olvl1 bit of tacr1 register #define olvl2 2 ; olvl2 bit of tacr1 register words period equ $34e2 ; for the period duty0 equ 0000 duty25 equ {period/4} duty50 equ {period/2} duty75 equ {duty25+duty50}
8/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle ;*************** ********************************************************* ; program code ;*************** ********************************************************* segment 'ram0' bytes .state ds.b 1 ; conversion step flag segment 'rom' words ; define subsequent addresses as words ; meaning that all instru ctions are located ; in the address field after 0ffh in the st72251 ; memory mapping ;--------------- --------------------------------------------------------- ; routine name : true ; input/output : x for pwm pulse length msb, a for pwm pulse length lsb ; / taoc1r,tacr1 bit 2 (output level 2) ; description : generation of true 100%, true 0% duty cycle and 5 timer-tick shift ;--------------- --------------------------------------------------------- .true bres tacr1,#olvl1 ; reload the default value of olvl1 bset tacr1,#olvl2 ; reload the default value of olvl2 tnz a ; test if pwm pulse length lsb=0 ? jrne go1 .go tnz x ; test if pwm pulse length msb=0 ? jrne go1 bres tacr1,#olvl2 ; to have a true 0% duty cycle ret .go1 cp a,#period.l ; test if pwm pulse length lsb=period lsb ? jrne cont1 cp x,#period.h ; test if pwm pulse length msb=period msb ? jrne cont1 bset tacr1,#olvl1 ; to obtain true 100% duty cycle ret .cont1 sub a,#5 ; subtraction of 5 timer ticks jrnc cont ; to have the true pulse length dec x .cont ld taoc1hr,x ld taoc1lr,a ret ;--------------- ---------------------------------------------------------
9/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle ; routine name : init_pwm ; input/output : / tacr1, tacr2, paddr, paor, miscr ; description : timer configuration for pwm generation with overflow ; interrupt turned on, and no other interrupts allowed (input capture, output ;compare) ;--------------- --------------------------------------------------------- .init_pwmld a,#$04 ; olvl2 = 1, olvl1 = 0 ld tacr1,a ; no other interrupt enabled. ld a,#$98 ; output on ocmp1 pin enabled and pwm mode selected. ld tacr2,a ; timer clock = fcpu/8 (1us if fcpu=8mhz) ; $94 for fcpu/2 and $90 for fcpu/4 bres paddr,#0 ; configuration of pa0 in floating input with bset paor,#0 ; interrupt ld a,#$10 ; miscellaneous register interrupt generation ld miscr,a ; on falling edge only ret ;--------------- --------------------------------------------------------- ; routine name : init_prog ; input/output : period/taoc1r, taoc2r, oldx, oldy ; description : to begin the prog with the default 100% duty cycle ; period=pulse length -> one timer tick pulse ; comments : the timer reset value is fffch so to have the true values ; we subtract 5 timer ticks ;--------------- --------------------------------------------------------- .init_prog ; to get right at the first ext0_it clr state bset state,#up/down; duty cycle sequence in decreasing order at first bset state,#4 ; to obtain true 100% after the first it ;to begin with the default 100% duty cycle (period=pulse-> 1 cpu pulse) ld a,#period.l ld y,#period.h sub a,#5 ;because of the timer reset value which is fffch jrnc sup dec y .sup ld taoc2hr,y ; load the msb of the pwm period ld taoc2lr,a ; load the lsb of the pwm period ld taoc1hr,y ; load the msb of the pwm period ld taoc1lr,a ; load the lsb of the pwm period ret ;*************** ************************************************************
10/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle ;* * ;* main-routine section * ;* * ;*************** ************************************************************ .main call init_pwm call init_prog rim ; enable interrupt (i=0 in ccr) .loop jra loop ; wait for timer interru pt ; ********************************************** ;* * ; * interrupt sub-routines library section * ;* * ; ********************************************** .dummy iret .sw_rt iret .ext0_rt btjf state,#4,bit3 ; state x001 0000->100% ld x,#period.h ; copy of the msb of the period ld a,#period.l ; copy of the msb of the period jra start .bit3 btjf state,#3,bit2 ; state lsb 1000-> 75% ld x,#duty75.h ; copy of duty cycle 75% msb ld a,#duty75.l ; copy of duty cycle 75% lsb jra start .bit2 btjf state,#2,bit1 ; state lsb 0100-> 50% ld x,#duty50.h ; copy of duty cycle 50% msb ld a,#duty50.l ; copy of duty cycle 50% lsb jra start .bit1 btjf state,#1,bit0 ; state lsb 0010-> 25% ld x,#duty25.h ; copy of duty cycle 25% msb ld a,#duty25.l ; copy of duty cycle 25% lsb jra start .bit0 btjf state,#0,else ; state lsb 0001-> 0% ld x,#duty0.h ld a,#duty0.l jra start .else ld a,#%10010000 ; reload state with its default value ld state,a iret .start call true btjf state,#up/down,down ; up/down=1 to increase up/down=0 to decrease
11/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle btjf state,#4,out clr state ; to decrease at the next it bset state,#3 ; to have 75% at the next it iret .out sla state ; to obtain the good value at the next it bset state,#up/down ; to keep the up/down bit iret .down btjt state,#0,out sra state ; to obtain the good value at the next it iret .ext1_rt iret .spi_rt iret .tima_rt iret .timb_rt iret .i2c_rt iret segment 'vectit' dc.w dummy ;ffe0-ffe1h location dc.w dummy ;ffe2-ffe3h location .i2c_it dc.w i2c_rt ;ffe4-ffe5h location dc.w dummy ;ffe6-ffe7h location dc.w dummy ;ffe8-ffe9h location dc.w dummy ;ffea-ffebh location dc.w dummy ;ffec-ffedh location .timb_it dc.w timb_rt ;ffee-ffefh location dc.w dummy ;fff0-fff1h location .tima_it dc.w tima_rt ;fff2-fff3h location .spi_it dc.w spi_rt ;fff4-fff5h location dc.w dummy ;fff6-fff7h location .ext1_it dc.w ext1_rt ;fff8-fff9h location .ext0_it dc.w ext0_rt ;fffa-fffbh location .softit dc.w sw_rt ;fffc-fffdh location .reset dc.w main ;fffe-ffffh location ; this last line refers to the first line. ; it used by the compiler/linker to determine code zone end ; be aware of the fact that the end directive should not ; be on the left of the page like the label names.
12/12 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http:/ /www.st.com

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